Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The storage elements are formed from two ferromagnetic layers separated by a tunneling layer. One of the two layers has at least one pinned magnetic polarization (or fixed layer) set to a particular polarity. The magnetic polarity of the other magnetic layer (or free layer) is altered to represent either a “1” (e.g., anti-parallel to the fixed layer) or “0” (e.g., parallel to the fixed layer). One such device having a fixed layer, a tunneling layer, and a free layer is a magnetic tunnel junction (MTJ). The electrical resistance of an MTJ is dependent on the magnetic polarity of the free layer compared to the magnetic polarity of the fixed layer. A memory device such as MRAM is built from an array of individually addressable MTJs.
FIG. 1 is a circuit schematic illustrating a portion of a conventional magnetic random access memory (MRAM). An MRAM 100 is divided into a data circuit 160, and reference circuits 140, 110, each circuit 110, 140, 160 including multiple bit cells 112, 126 (only a single bit cell is illustrated to facilitate understanding). During read out of the bitcell of the data circuit 160, the resistance of the magnetic tunnel junction is compared to the effective resistance of the reference parallel MTJ of the reference circuit 110 connected in parallel with the reference anti-parallel bitcell of the reference circuit 140. Resistance of the bitcells are measured by applying a source voltage and determining an amount of current flowing through the bitcells. For example, in the bitcell of the parallel reference circuit 110, a current source 120 is applied to a magnetic tunnel junction (MTJ) 112 by read select transistors 122, 124, and a word line select transistor 126. The MTJ 112 includes a fixed layer 114, tunneling layer 116, and a free layer 118. When the free layer 118 and the fixed layer 114 have magnetizations aligned substantially parallel, the resistance of the MTJ 112, and thus the bitcell 110, is low. When the free layer 118 and the fixed layer 114 have magnetizations aligned substantially anti-parallel, the resistance of the MTJ 112, and thus the bitcell 110, is high.
Bitcells of a magnetic random access memory may be arranged in one or more arrays including a pattern of memory elements (e.g. MTJ in case of MRAM). STT-MRAM (Spin-Transfer-Torque Magnetic Random Access Memory) is an emerging nonvolatile memory and its advantages of non-volatility, comparable speed to eDRAM (Embedded Dynamic Random Access Memory), smaller chip size compared to eSRAM (Embedded Static Random Access Memory), unlimited read/write endurance, and low array leakage current have opened a great opportunity to STT-MRAM (Spin-Transfer-Torque Magnetic Random Access Memory) as a universal working memory in SoC (System on Chip) design. Key design challenges of STT-MRAM in SoCs are to ensure reliable operations with very low read-disturbance failure rate and high macro yield from robust design.
A disturbance-free read scheme with short WL (Word Line) pulse and lower WL voltage during read operation has been proposed as one method of reducing read disturbance failures and increasing macro yield. However, implementation of such a dual-voltage WL driver increases chip size and delays read speed due to the lower WL voltage during read operations. Moreover, reference cells using the reference WL scheme are more frequently accessed than normal cells and are more susceptible to read-disturbance issues.